Noise rejection circuitry

ABSTRACT

Noise rejection circuitry sutable for detection of a resonant tag in an electronic security system especially adapted for use in retail stores. True signals are distinguished from noise by sensing the absence of one or more pulses in an expected chain of pulses produced by the resonant tag. A parallel noise inhibit function is provided by a staircase generator and comparator which prevent an alarm indication in response to received fast pulse noise.

Elite tates 8e 8 11 1 1111 31 9 Lichtblau Aug, 6, 1974 [54] NOISEREJECTION CIRCUITRY 3,696,379 10 1972 Minasy 340/280 [76] Inventor:George Jay Lichtblau 425 63rd 3,752,960 8/1973 Walton 340/152 J t. N Yk, N.Y. 10021 s ew or Primary ExaminerDavid L. Trafton Flledl g- 1973Attorney, Agent, or Firm-Weingarten, Maxham & 21 Appl. No.: 389,728Schurgm 52 us. 01. 340/280, 340/152 J, 340/258 0, [57] ABSTRACT 343/6555 Noise rejection circuitry sutable for detection of a res- [51] Int.Cl. G08b 13/24- Onant t i an l t o i e urity system especially Field MSearch 340/258 152 adapted for use in retail stores. True signals aredistin- 343/6.5 R, SS guished from noise by sensing the absence of oneor more pulses in an expected chain of pulses produced References Citedby the resonant tag. A parallel noise inhibit function is UNITED STATESPATENTS provided by a staircase generator and comparator 3,115,62212/1963 Jaffe 340/224 which Prevent an alarm indication in response to3,500,373 3/1970 Minasy 340/280 x Ceived fast Pulse noise. 3,52l,2807/1970 .lanco et al. t 1 343/65 SS 3,624,631 11 1971 Chomet et al. 340280 14 Claims, 6 Drawmg Flgul'es 1o 14 12 15 /l6 1 2o 2 2 24 s R F R FSIGNAL NOISE TRANSMITTER a 5F 4, DET. PROCESSING REJECTION 4, ALARM 3CIRCUITRY CIRCUITRY NOISE REJECTION CIRCUITRY FIELD OF THE INVENTIONThis invention relates to noise rejection circuitry and moreparticularly to circuitry for the reliable and rapid detection of aresonant tag circuit within a controlled area.

BACKGROUND OF THE INVENTION Electronic security systems are known forpreventing unauthorized removal of articles from an area underprotection. Such systems are especially suitable for use in retailstores to prevent the theft of articles from the store and to minimizeconsiderable losses occasioned by shoplifting. A particularly effectivesystem is described in copending application Serial No. 214,361 whereina multi-frequency resonant tag is provided having different frequenciesfor detection and deactivation. The resonant tag circuit is operative ata first frequency to permit detection by electromagnetic interrogationthereof, and is operative at a second frequency to permit deactivationthereof by an applied electromagnetic field which destroys the resonantproperty of the circuit at its detection frequency. The system of thecopending application includes noise rejection circuitry fordiscriminating true signals produced by a resonant tag in the detectionzone from spurious signal conditions caused by noise. This circuitrydetermines whether a predetermined number of pulses of selectedperiodicity are received within a selected time interval. If therequisite pulses are not received by the end of this interval, thecircuitry is then reset to prevent false alarm actuation and to renewthe detection cycle.

SUMMARY OF THE INVENTION In accordance with the present invention,improved noise rejection circuitry is provided for an electronicsecurity system in which an expected train of pulses of predeterminedperiodicity is sensed to provide an alarm indication, the circuitrybeing reset immediately upon detection of a missed pulse in the expectedtrain. Pulses are derived from signals produced by a resonant tagcircuit in the detection zone, and such pulses are applied to anonretriggerable gating circuit which inhibits pulses having other thanthe predetermined periodicity. The output of this gating circuit isapplied to a retriggerable circuit such as a multivibrator which acts asa missing pulse detector for resetting an associated integrator circuit.A staircase generator and comparator also receives the pulses derivedfrom the tag circuit and is operative to reset the integrator inresponse to noise pulses occurring at rates faster than the periodicityof expected pulses. The noise rejection circuitry of the invention thusprovides faster true pulse detection by resetting the integrator as soonas a missing pulse is detected, rather than awaiting termination of atiming cycle.

DESCRIPTION OF THE DRAWING The invention will be more fully understoodfrom the following detailed description taken in conjunction with theaccompanying drawing in which:

FIG. I is a block diagram representation of an electronic securitysystem in which the invention may be advantageously employed;

FIG. 2 is a block diagram representation of noise discriminationcircuitry according to the invention;

FIG. 3 is a block diagram representation of the nonretriggerablemonostable multivibrator of FIG. 2;

FIG. 4 is a block diagram representation of the retriggerable monostablemultivibrator of FIG. 2;

FIG. 5 is a schematic representation of the integrator and threshold ofFIG. 2; and

FIG. 6 is a plot of signal diagrams useful in illustrating the operationof the circuitry of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION The noise discrimination circuitof the invention may be advantageously employed in an electronicsecurity system such as that illustrated in FIG. I and which includes atransmitter 10 coupled to an antenna I2, typically a loop antenna,operative to provide an electromagnetic field within a predeterminedarea to be controlled. A receiving antenna 14, also typically a loopantenna, receives energy radiated by antenna 12 and is arranged forsensing of a resonant tag circuit 15 at the controlled area, couplingthe received energy to an RF front-end which includes an RF band passfilter 16 and an RF amplifier 18. The output of amplifier I8 is appliedto a detector 20, the output of which is, in turn,

coupled to signal processing circuitry 22. The signal processingcircuitry 22 can include analog noise limiting circuits such as filtersto define the band of received signals to be subsequently processed.Output signals from circuitry 22 are processed by noise rejectioncircuitry 24 which is the subject of the present invention. The outputof the noise rejection circuitry is operative to actuate an alarm 26 orother output utilization apparatus.

The noise rejection circuitry of the invention is depicted in blockdiagram form in FIG. 2 and includes a nonretriggerable monostablemultivibrator 28 receiving pulses from signal processing circuitry 22and which triggers a retn'ggerable monostable multivibrator 30. Theoutput of multivibrator 30 is integrated by an integrator 32, thisintegrated output signal being applied to a threshold detector 34. Ifthe threshold level provided by detector 34 is exceeded by the outputsignal from integrator 32, detector 34 provides an output signal toalarm 26 for actuation thereof. A staircase generator and comparator 36may additionally be employed to receive pulses from signal processingcircuitry 22 and to provide a reset signal to integrator 32 in responseto high frequency noise, as will be described.

The nonretriggerable multivibrator 28 is illustrated more particularlyin FIG. 3 and includes a flip flop 40 receiving a signal from signalprocessing circuitry 22 which is operative to set the flip flop in oneof its operative states. The flip flop 40 also receives a reset signalfrom a threshold detector 42 which is driven by an input signal derivedfrom an RC integrator comprising a resistor R1 and series connectedcapacitor C1 connected between a source of potential +V and a source ofreference potential, typically ground. A switch S1 is connected acrosscapacitor Cl and is operative in response to the output signal from flipflop 40) to shunt the capacitor to the reference potential.

When switch S1 is in its open condition, a voltage derived from source+V is effective to charge capacitor C1, the capacitor voltage beingoperative upon exceedance of a predetermined threshold voltage ofthreshold detector 42 to cause application of a reset signal to flipflop 49. When switch S1 is in its closed condition, capacitor C1 isdischarged to prevent exceedance of the threshold of detector 42 and tothereby prevent application of a reset signal to flip flop 40.

Upon receipt by flip flop 40 of a trigger pulse from signal processingcircuitry 22, flip flop 40 is set to a first state typically a highstate and thereby provides an output signal of a first level, typicallya higher signal level, to multivibrator 30, this output signal alsobeing operative to open switch S1 to permit charging of capacitor C1.When the voltage across capacitor C1 reaches a predetermined thresholdlevel, detector 42 is triggered to provide a reset signal to flip flop40 which, in turn, provides an output signal of second level, typicallya lower signal level, and which is operative to close switch S1. Theswitch S1 is typically a solid state switch such as a transistor havingits gate electrode coupled to the output of flip flop 40.

The flip flop 40 can only be triggered by alternate pulses applied tothe set and reset input terminals thereof and thus cannot be retriggereduntil completion of the timing cycle provided by the RC integrator inrelation to the threshold voltage of detector 42. Pulses received fromsignal processing circuitry 22 applied to the flip flop 40 during thecharging cycle of the capacitor C1 are not operative to affect the stateof flip flop 40 and are eliminated from subsequent processing.

The retriggerable monostable multivibrator 30 is shown more particularlyin FIG. 4 and is generally similar to the multivibrator circuit of FIG.3. A flip flop 50 receives a momentary set signal from multivibrator 28,specifically the leading edge of the received pulse, which also providesa momentary input signal via an OR gate 52 to a switch S2. The flip flop50 receives a reset signal from a threshold detector 54 which is drivenby an RC integrator network including a resistor R2 in series with acapacitor C2 and connected between a source of suitable potential +V anda source of reference potential, typically ground. The switch S2 isconnected in shunt across capacitor C2 and when closed is operative toshunt the capacitor to the reference potential. The output signal fromflip flop 50 is applied to integrator 32 and is also applied to an inputof OR gate 52.

Upon receipt of a trigger pulse from multivibrator 28, capacitor C2 isdischarged by momentary closure of switch S2 and flip flop t) is set toits first state to provide an output signal of first, typically high,output level. The output signal of first signal level is applied via ORgate 52 to switch S2 to cause opening thereof for so long as the outputsignal remains at its high level and no trigger signals are receivedfrom MV 28. Thus, pulses being received from multivibrator 28 ofpredetermined periodicity, periodically cause S2 to close, dischargingC2, and thus cause flip flop 50 to remain in its set condition toprovide a continuous output signal of constant level. Received pulsesfrom a valid tag circuit in the detection zone are predetermined to havethe selected periodicity to achieve this result.

In the event that a pulse from multivibrator 28 is not received withinthe interval provided by the charging time constant of the integratornetwork, switch S2 remains open to permit the capacitor C2 to charge toits triggering level causing threshold detector 54 to provide a resetsignal to flip flop 50. The flip flop provides in its reset state anoutput signal of second level, typically a low voltage, which signalsthe detection of a missed pulse. Thus, the multivibrator 30 functions asa missing pulse detector to cause resetting of the detection circuitryto prevent a spurious alarm indication of tag presence and to commenceanother detection cycle.

The integrator 32 and threshold detector 34 are illustrated in typicalschematic form in FIG. 5. The integrator includes a resistor R3 inseries with a capacitor C3, the resistor being operative to receivesignals from multivibrator 30 while the capacitor is coupled to a groundor other reference potential. A diode D1 is connected with the polarityshown across resistor R3. A switching device, typically a transistor Q1,is connected with the collector connected to the junction betweenresistor R3 and capacitor C3 and the emitter connected to ground orreference potential. A bias resistor R4 is connected between the baseand emitter electrodes of transistor Q1, and the base electrode is alsooperative to receive a reset signal from the staircase generator (FIG.2).

The threshold detector includes a voltage divider network including aresistor R5 connected from a source of potential +V to the sourceelectrode of a unijunction transistor Q2, the drain electrode of whichis connected via a resistor R6 to ground or other reference potential.The gate electrode of transistor Q2 is connected to the junction betweencapacitor C3 and resistor R3. An output signal is coupled from thesource electrode of transistor Q2. It will be appreciated that if anoutput signal of opposite polarity is desired, such output can bederived from the drain electrode of transistor Q2.

In response to the output from multivibrator 30 of high signal level,capacitor C3 charges via resistor R3 to a reference potential at whichtransistor Q2 is triggered to its conductive state to provide an outputsignal at the output terminal thereof for alarm actuation. The diode D1is reverse biased by the voltage across resistor R3. If multivibrator 30(FIG. 2) is reset to provide an output voltage of lower level, capacitorC3 will discharge through diode Dll and thus the voltage acrosscapacitor C3 will be at the lower voltage level then being provided bymultivibrator 30, and which is chosen to be below the threshold level atwhich transistor Q2 becomes conductive. As a result, no output signalappears from the threshold detector and no alarm is produced. Theintegrator 32 can also be reset from pulses provided from staircasegenerator and comparator 36 to prevent triggering of transistor Q2 whichcould provide spurious output signals. Upon receipt of a reset signal,transistor Q1 is caused to conduct and thus shunt capacitor C3 to groundor other reference potential. The capacitor C3 is thereby dischargedduring the interval of the reset signal to delay actuation of transistorQ2 and the resulting output signal for alarm actuation.

Staircase generator and comparator 36, which may be employed in theinvention, is operative to apply a reset signal to integrator 32. Inresponse to trigger pulses from signal processing circuitry 22, thestaircase generator produces a staircase voltage which rises during theduration of each pulse from circuitry 22. The comparator contains athreshold circuit and upon exceedance of a predetermined threshold levelby the staircase signal, an output pulse is produced to reset integrator32, and also to reset the staircase generator itself. ln addition, thestaircase generator may be reset by a signal from the integrator 32 orfrom threshold detector 34 to permit proper processing of subsequentlyreceived pulses. The voltage characteristics of the staircase generatorare determined such that the staircase generator threshold requires agreater number of pulses to produce a reset signal than does theintegrator to produce an alarm signal.

The operation .of the circuit in FIG. 2 will be described in conjunctionwith the signal diagrams of FIG. 6. The pulses from the tag sensingcircuitry, such as from circuitry 22 of FIG. 1, are depicted in FIG. 6A.These pulses are applied to the nonretriggerable monostablemultivibrator 28, which has a period Tl slightly less than the period ofthe modulation rate. The leading edge of T1 triggers multivibrator whilemultivibrator 28 is operative to inhibit spurious input signals fromtriggering multivibrator 30 at a rate faster than that of the expectedsignal, as illustrated in FIG. 6B.

Multivibrator 30 is a retriggerable monostable multivibrator with anormal timing period T2 slightly greater than the period of the expectedsignals. Each time multivibrator 30 receives a trigger pulse frommultivibrator 28, multivibrator 30 is reset to its initial timing stateand remains in its high voltage output state for a period T2 secondsafter the last trigger pulse. FIG. 6C illustrates the output ofmultivibrator 30 provided that the trigger pulses occur with a periodless than T2. The timing capacitor C2 voltage is depicted in FIG. 6D. Aslong as the capacitor voltage is discharged prior to exceeding thethreshold voltage, multivibrator 30 will remain in its high voltagestate.

As long as multivibrator 30 is in its high voltage state, the outputvoltage will be applied to the integrator and will generate a rampsignal from the integrator, as shown in FIG. 6E. If the integratoroutput voltage exceeds the threshold level, the alarm will be actuated.However, if multivibrator 30 should return to its low voltage stateprior to time T3, the integration time of integrator 32, the integratorwill be reset thereby preventing the threshold voltage from beingexceeded and preventing alarm actuation.

Thus, the alarm can be actuated only if multivibrator 30 receives acontinuous stream of trigger pulses with a period t, where T1 t T2, andwhere these pulses arrive continuously for a time period greater thanT3. In the system shown in FIG. 2, the first pulse that is missed" bymultivibrator 30 will reset the entire system. Alternatively,multivibrator 30 may be modified so that more than one pulse must bemissed before the integrator will be reset.

A major advantage of the circuitry of the invention is the provision ofimmediate reset of the pulse integrator upon detection of a missingpulse. For example, if the detection system receives noise signals justprior to the detection of an actual resonant tag, the system will resetitself immediately upon cessation of the spurious signal and willimmediately begin integration of real pulses for alarm actuation.Additionally, by detecting missing pulses in a train of expected pulsesof predetermined periodicity, the integration period of the circuitry isnot related to the reset speed of the detector.

Thus, a longer integration period may be used to increase noiserejection without thereby decreasing the reset speed of the detectorupon receipt of spurious sig- 65 tive such as if the reset period wereshorter. In the circuitry of the invention, the primary reset functionis independent of the integration period and will permit detectionnotwithstanding variation in the integration period.

It should be apparent that the invention can be implemented by variouscircuits other than those disclosed to accomplish the intended purpose.Accordingly, it is not intended to limit the invention by what has beenparticularly shown and described except as indicated in the appendedclaims.

What is claimed is:

1. For use in an electronic security system which includes means forproviding in a surveillance zone an electromagnetic field of a frequencywhich is swept within a predetermined range, and means for detecting thepresence of a resonant tag circuit having a frequency within said range,circuitry for discriminating between the presence of a valid tag circuitin said surveillance zone and spurious signals, said circuitrycomprising:

means for receiving a train of pulses derived from detection of a tagcircuit within said surveillance zone;

means operative upon receipt of a predetermined number of pulses ofpredetermined periodicity to provide an alarm indication; and

means for resetting said circuitry immediately upon detection of atleast one missed pulse in the expected train of pulses.

2. A circuit according to claim 1 including staircase generating meansoperative in response to the output pulses from said detecting means togenerate a staircase signal which increases in amplitude; and

means for providing a reset signal to said circuitry upon the exceedanceby said staircase signal of a predetermined threshold level.

3. For use in an electronic security system which includes means forproviding in a surveillance zone an electromagnetic field of a frequencywhich is swept within a predetermined range, and means for detecting thepresence of a resonant tag circuit having a resonant frequency withinsaid range and for providing pulses in response thereto, noise rejectioncircuitry for distinguishing between pulses provided by said tag circuitand pulses caused by spurious conditions, said noise rejection circuitrycomprising:

a nonretriggerable gating circuit receiving pulses from said detectingmeans and operative to provide output pulses in response to receivedpulses of predetermined periodicity;

a retriggerable circuit operative in response to the output pulses fromsaid nonretriggerable gating circuit;

integrator means operative in response to the output pulses from saidretriggerable circuit to provide an integrated signal; and thresholddetector means having a predetermined threshold level and operative toprovide an output signal for alarm actuation upon exceedance of saidthreshold level by said integrated signal.

4. Noise rejection circuitry according to claim 3 and including:

staircase generating means operative in response to the output pulsesfrom said detecting means to generate a staircase signal which increasesin amplitude in the presence of each of said output pulses and operativeto provide a reset signal upon the exceedance by said staircase signalof a predetermined threshold level.

5. Noise rejection circuitry according to claim 3 wherein saidretriggerable circuit provides output signal of first or second signalstate to said integrator means.

6. Noise rejection circuitry according to claim 3 wherein saidretriggerable circuit provides an output signal of first voltage levelin response to a continuous train of pulses of predetermined periodicityfrom said nonretriggerable gating circuit, and provides an output signalof second voltage level in response to the absence of at'least one pulsein said train of pulses.

7. Noise rejection circuitry according to claim 6 wherein saidintegrator means includes means operative in response to said outputsignal of first voltage level to provide an integrated output signal foralarm actuation; and

means response to said output signal of second voltage level to resetsaid integrator.

8. Noise rejection circuitry according to claim 7 wherein said firstvoltage level is greater than said second voltage level.

9. Noise rejection circuitry according to claim 3 wherein-saidnonretriggerable gating circuit and said retriggerable circuit are eachmultivibrators.

10. Noise rejection circuitry according to claim 3 wherein'saidnonretriggerable gating circuit includes an RC circuit;

a threshold detector operative in response to a predetermined voltage onthe capacitor of said RC circuit; and

a flip flop operative to receive trigger pulses from said tag circuitand a reset signal from said threshold detector and to provide an outputsignal to said retriggerable circuit upon receipt of said triggerpulses.

11. Noise rejection circuitry according to claim 3 wherein saidretriggerable circuit includes a flip flop;

an RC circuit;

a switch operative to control the charging of the capacitor in said RCcircuit; and

a threshold detector operative to provide a reset signal to said flipflop in response to a predetermined voltage level across said capacitor;

means for simultaneously providing from said nonretriggerable gatingcircuit a set signal to said flip flop and an input signal to saidswitch;

said switch being operative in response to said input signal to groundsaid capacitor and thereby prevent said threshold detector fromproviding a reset signal to said flip flop for a period of time greaterthan the minimum interval between pulses received from saidnonretriggerable gating circuit.

12. Noise rejection circuitry according to claim 7 wherein saidintegrator means includes:

an RC circuit driven by the output voltage of said retriggerablecircuit;

solid state gating means operative to provide an output signal for alarmactuation in response to a predetermined voltage; and

" diode means conductive in response to signals from 13. An electronicsecurity system comprising transmitter means for providing anelectromagnetic field in a surveillance zone at a frequency repetitivelyswept through a predetermined range;

a multi-resonant tag circuit having a first resonant frequency withinsaid predetermined range of frequencies and a second resonant frequencyoutside of said predetermined range of frequencies;

receiver means for detecting the presence of said first resonantfrequency from a tag circuit present in said surveillance zone;

said receiver means including detector means operative to provide outputpulses in response to the presence of the first resonant frequency ofsaid tag circuit in said electromagnetic field;

noise rejection circuitry operative in response to pulses from saiddetector means for distinguishing between pulses provided by said tagcircuit and pulses caused by spurious conditions, said circuitrycomprising:

means for receiving a train of pulses derived from de tection of a tagcircuit within said surveillance zone;

means operative upon receipt of a predetermined number of pulses ofpredetermined periodicity to provide an alarm indication; and

means for resetting said circuitry immediately upon detection of atleast one missed pulse in the expected train of pulses.

14. An electronic security system according to claim 13 wherein saidmeans operative upon receipt of a predetermined number of pulses ofpredetermined periodicity includes integrator means for providing anintegrated output signal in response to said pulses of predeterminedperiodicity; and

threshold detector means operative to provide an output signal uponreceipt of an integrated output signal of predetermined magnitude;

and wherein said resetting means includes a retriggerable circuitoperative to receive pulses having a predetermined minimum period and toprovide an output voltage of a first voltage level to said integratormeans in response to a continuous train of pulses having less than apredetermined period and to provide an output voltage of a secondvoltage level to said integrator means in response to a missed pulse.

1. For use in an electronic security system which includes means forproviding in a surveillance zone an electromagnetic field of a frequencywhich is swept within a predetermined range, and means for detecting thepresence of a resonant tag circuit having a frequency within said range,circuitry for discriminating between the presence of a valid tag circuitin said surveillance zone and spurious signals, said circuitrycomprising: means for receiving a train of pulses derived from detectionof a tag circuit within said surveillance zone; means operative uponreceipt of a predetermined number of pulses of predetermined periodicityto provide an alarm indication; and means for resetting said circuitryimmediately upon detection of at least one missed pulse in the expectedtrain of pulses.
 2. A circuit according to claim 1 including staircasegenerating means operative in response to the output pulses from saiddetecting means to geneRate a staircase signal which increases inamplitude; and means for providing a reset signal to said circuitry uponthe exceedance by said staircase signal of a predetermined thresholdlevel.
 3. For use in an electronic security system which includes meansfor providing in a surveillance zone an electromagnetic field of afrequency which is swept within a predetermined range, and means fordetecting the presence of a resonant tag circuit having a resonantfrequency within said range and for providing pulses in responsethereto, noise rejection circuitry for distinguishing between pulsesprovided by said tag circuit and pulses caused by spurious conditions,said noise rejection circuitry comprising: a nonretriggerable gatingcircuit receiving pulses from said detecting means and operative toprovide output pulses in response to received pulses of predeterminedperiodicity; a retriggerable circuit operative in response to the outputpulses from said nonretriggerable gating circuit; integrator meansoperative in response to the output pulses from said retriggerablecircuit to provide an integrated signal; and threshold detector meanshaving a predetermined threshold level and operative to provide anoutput signal for alarm actuation upon exceedance of said thresholdlevel by said integrated signal.
 4. Noise rejection circuitry accordingto claim 3 and including: staircase generating means operative inresponse to the output pulses from said detecting means to generate astaircase signal which increases in amplitude in the presence of each ofsaid output pulses and operative to provide a reset signal upon theexceedance by said staircase signal of a predetermined threshold level.5. Noise rejection circuitry according to claim 3 wherein saidretriggerable circuit provides output signal of first or second signalstate to said integrator means.
 6. Noise rejection circuitry accordingto claim 3 wherein said retriggerable circuit provides an output signalof first voltage level in response to a continuous train of pulses ofpredetermined periodicity from said nonretriggerable gating circuit, andprovides an output signal of second voltage level in response to theabsence of at least one pulse in said train of pulses.
 7. Noiserejection circuitry according to claim 6 wherein said integrator meansincludes means operative in response to said output signal of firstvoltage level to provide an integrated output signal for alarmactuation; and means response to said output signal of second voltagelevel to reset said integrator.
 8. Noise rejection circuitry accordingto claim 7 wherein said first voltage level is greater than said secondvoltage level.
 9. Noise rejection circuitry according to claim 3 whereinsaid nonretriggerable gating circuit and said retriggerable circuit areeach multivibrators.
 10. Noise rejection circuitry according to claim 3wherein said nonretriggerable gating circuit includes an RC circuit; athreshold detector operative in response to a predetermined voltage onthe capacitor of said RC circuit; and a flip flop operative to receivetrigger pulses from said tag circuit and a reset signal from saidthreshold detector and to provide an output signal to said retriggerablecircuit upon receipt of said trigger pulses.
 11. Noise rejectioncircuitry according to claim 3 wherein said retriggerable circuitincludes a flip flop; an RC circuit; a switch operative to control thecharging of the capacitor in said RC circuit; and a threshold detectoroperative to provide a reset signal to said flip flop in response to apredetermined voltage level across said capacitor; means forsimultaneously providing from said nonretriggerable gating circuit a setsignal to said flip flop and an input signal to said switch; said switchbeing operative in response to said input signal to ground saidcapacitor and thereby prevent said threshold detector from providIng areset signal to said flip flop for a period of time greater than theminimum interval between pulses received from said nonretriggerablegating circuit.
 12. Noise rejection circuitry according to claim 7wherein said integrator means includes: an RC circuit driven by theoutput voltage of said retriggerable circuit; solid state gating meansoperative to provide an output signal for alarm actuation in response toa predetermined voltage; and diode means conductive in response tosignals from said retriggerable circuit of said lower voltage level andoperative to prevent the voltage across the capacitor in said RC circuitfrom reaching a voltage required to activate said solid state gatingmeans.
 13. An electronic security system comprising transmitter meansfor providing an electromagnetic field in a surveillance zone at afrequency repetitively swept through a predetermined range; amulti-resonant tag circuit having a first resonant frequency within saidpredetermined range of frequencies and a second resonant frequencyoutside of said predetermined range of frequencies; receiver means fordetecting the presence of said first resonant frequency from a tagcircuit present in said surveillance zone; said receiver means includingdetector means operative to provide output pulses in response to thepresence of the first resonant frequency of said tag circuit in saidelectromagnetic field; noise rejection circuitry operative in responseto pulses from said detector means for distinguishing between pulsesprovided by said tag circuit and pulses caused by spurious conditions,said circuitry comprising: means for receiving a train of pulses derivedfrom detection of a tag circuit within said surveillance zone; meansoperative upon receipt of a predetermined number of pulses ofpredetermined periodicity to provide an alarm indication; and means forresetting said circuitry immediately upon detection of at least onemissed pulse in the expected train of pulses.
 14. An electronic securitysystem according to claim 13 wherein said means operative upon receiptof a predetermined number of pulses of predetermined periodicityincludes integrator means for providing an integrated output signal inresponse to said pulses of predetermined periodicity; and thresholddetector means operative to provide an output signal upon receipt of anintegrated output signal of predetermined magnitude; and wherein saidresetting means includes a retriggerable circuit operative to receivepulses having a predetermined minimum period and to provide an outputvoltage of a first voltage level to said integrator means in response toa continuous train of pulses having less than a predetermined period andto provide an output voltage of a second voltage level to saidintegrator means in response to a missed pulse.